求助!!针对sparkroad开发版,官方提供了一个sdram摄像头的例程,数据传输是:写fifo→sdram→读fifo,因为我自己的工程涉及到时序问题,所以针对这一块单独做一下验证。fifo+sdram控制器部分是用的demo-ov2640_sdram里的Sdrm_Control_4Port。每次读写突发256个数据,当输入256-512这256个数据时,数据从写fifo→sdram →读fifo传输都没问题,但是读fifo输出端口输出的数据就出现了问题,起始数据应该是从256开始,但是第一个输出的是356,当我用其他数据测试的时候也是往后了100个数据。(或者刚开始传入读fifo的时候数据就丢了100个?)
随机指定256个数据输入,比如256-512或1280-1536。
系统时钟25MHz,读写突发长度为256时,其余配置按照例程不变,上板用CWC抓取波形如下:
当读写突发长度改为128后,开始独处的数据变成了从356开始:
数据生成及读写使能代码如下:
`include "Sdram_Params.h"
module top_text2
#(
parameter CNT_MAX = 12'd2048
)
(
input wire clk_25,
input wire RESET_N,
output wire [31:0] data_out
);
//===========写fifo============
reg [31:0] tx_cnt; /* synthesis keep */
reg wr_en_r;
wire wr_en; /* synthesis keep */
wire [31:0] data_in; /* synthesis keep */
reg [31:0] data_in_r; /* synthesis keep */
//===========读fifo============
wire rd_en; /* synthesis keep */
reg rd_en_r;
always @(posedge clk_25)
if(!RESET_N)
tx_cnt <= 1'b0;
else if (tx_cnt == CNT_MAX -1)
tx_cnt <= 1'b0;
else
tx_cnt <= tx_cnt + 1'b1;
//=================突发读写256测试================//
assign wr_en = wr_en_r;
assign rd_en = rd_en_r;
always @(posedge clk_25)
begin
if(!RESET_N)
begin
rd_en_r <= 1'b0;
wr_en_r <= 1'b0;
data_in_r <= 1'b0;
end
else if (tx_cnt[10:8] == 3'b001) //256-512
begin
rd_en_r <= 1'b0;
wr_en_r <= 1'b1;
data_in_r <= tx_cnt;
end
else if (tx_cnt[10:8] == 3'b011) //768-1024
begin
rd_en_r <= 1'b1;
wr_en_r <= 1'b0;
data_in_r <= 1'b0;
end
else if (tx_cnt[10:8] == 3'b101) //1280-1536
begin
rd_en_r <= 1'b0;
wr_en_r <= 1'b1;
data_in_r <= tx_cnt;
end
else if (tx_cnt[10:8] == 3'b111) //1792-2048
begin
rd_en_r <= 1'b1;
wr_en_r <= 1'b0;
data_in_r <= 1'b0;
end
else
begin
rd_en_r <= 1'b0;
wr_en_r <= 1'b0;
data_in_r <= 1'b0;
end
end
assign data_in = data_in_r;
Top_sdram u_Top_sdram
(
.clk_25 (clk_25) ,
.RESET_N (RESET_N) , //System Reset
// FIFO Write Side 1
.WR1_DATA (data_in) , //Data input
.WR1 (wr_en) , //Write Request
.WR1_ADDR (21'b0) , //Write start address
.WR1_MAX_ADDR (21'd1024) , //Write max address
.WR1_LENGTH (10'd256) , //Write length
// .WR1_LENGTH (9'd128) , //Write length
.WR1_LOAD (~RESET_N) , //Write register load & fifo clear
.WR1_CLK (clk_25) , //Write fifo clock
.WR1_FULL () , //Write fifo full
.WR1_USE () , //Write fifo usedw
// FIFO Read Side 1
.RD1_DATA (data_out) , //Data output
.RD1 (rd_en) , //Read Request
.RD1_ADDR (21'b0) , //Read start address
.RD1_MAX_ADDR (21'd1024) , //Read max address
.RD1_LENGTH (10'd256) , //Read length
// .RD1_LENGTH (9'd128) , //Read length
.RD1_LOAD (~RESET_N) , //Read register load & fifo clear
// .RD1_CLK () , //Read fifo clock
.RD1_EMPTY () , //Read fifo empty
.RD1_USE () //Read fifo usedw
);
endmodule