Simple FSM 1 asynchronous reset))
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
//声明了这是一个组合逻辑电路
// State transition logic
case(state)
A:begin
if(in) begin
next_state=A;
end
else begin
next_state=B;
end
end
B:begin
if(in) begin
next_state=B;
end
else begin
next_state=A;
end
end
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
//实现异步复位
// State flip-flops with asynchronous reset
if(areset)begin
state<=B;
end
else begin
state<=next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out=(state==B);
endmodule
按照《夏宇闻 Verilog》P 169 书写即可
Simple FSM 1 synchronous reset
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
parameter A=0,B=1;
// Fill in state name declarations
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state<=B;
out<=1'b1;
end
else begin
case (present_state)
// Fill in state transition logic
A:begin
if(in)begin
present_state<=A;
out<=1'b0;
//present_state<=next_state;
end
else begin
present_state<=B;
out<=1'b1;
//present_state<=next_state;
end
end
B:begin
if(in)begin
present_state<=B;
out<=1'b1;
//present_state<=next_state;
end
else begin
present_state<=A;
out<=1'b0;
//present_state<=next_state;
end
end
endcase
end
end
endmodule
module top_module(
input clk,
input reset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
case(state)
A:begin
if(in == 1'b1)begin
next_state = A;
end
else begin
next_state = B;
end
end
B:begin
if(in == 1'b1)begin
next_state = B;
end
else begin
next_state = A;
end
end
endcase
end
always @(posedge clk) begin // This is a sequential always block
if(reset)begin
state <= B;
end
else begin
state <= next_state;
end
end
// Output logic
assign out = (state == B);
endmodule
将第一题的异步触发改为同步触发即可，第一个自己写的也可以，但是谨慎使用
6.3 Verilog 状态机 | 菜鸟教程 (runoob.com) 一段、二段、三段状态机的编写
Simple FSM 2 asynchromous reset
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
ON:begin
if(k==0)begin
next_state<=ON;
end
else if(k==1)begin
next_state<=OFF;
end
end
OFF:begin
if(j==1)begin
next_state<=ON;
end
else begin
next_state<=OFF;
end
end
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state<=OFF;
end
else begin
state<=next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out=(state==ON);
endmodule
Simple FSM 2 synchromous reset
module top_module(
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
ON:begin
if(k==0)begin
next_state<=ON;
end
else if(k==1)begin
next_state<=OFF;
end
end
OFF:begin
if(j==1)begin
next_state<=ON;
end
else begin
next_state<=OFF;
end
end
endcase
end
always @(posedge clk) begin
// State flip-flops with asynchronous reset
if(reset)begin
state<=OFF;
end
else begin
state<=next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out=(state==ON);
endmodule
Simple state transitions 3
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
always@(*)begin
case(state)
A:begin
if(in)begin
next_state=B;
end
else begin
next_state=A;
end
end
B:begin
if(in)begin
next_state=B;
end
else begin
next_state=C;
end
end
C:begin
if(in)begin
next_state=D;
end
else begin
next_state=A;
end
end
D:begin
if(in)begin
next_state=B;
end
else begin
next_state=C;
end
end
endcase
end
assign out=(state==D);
// State transition logic: next_state = f(state, in)
// Output logic: out = f(state) for a Moore state machine
endmodule
Simple one-hot state transition 3
单热状态机编码保证正好一个状态位为 1。这意味着可以通过仅检查一个状态位而不是所有状态位来确定状态机是否处于特定状态。这通过检查状态转换图中每个状态的传入边，得出状态转换的简单逻辑方程。
比如在上面的状态机上，状态机怎么能达到状态A呢？它必须使用两个传入边之一：“当前处于状态 A 且 in=0”或“当前处于状态 C 且 = 0”。由于采用独热编码，测试“当前处于状态 A”的逻辑方程只是状态 A 的状态位。这导致了状态位 A 的下一个状态的最终逻辑方程：。独热编码保证一次最多有一个子句（产品术语）处于“活动状态”，因此这些子句可以一起 OR 连接。next_state[0] = state[0]&(~in) | state[2]&(~in)
当练习要求“通过检查”状态转换方程时，请使用此特定方法。法官将使用非一热输入进行测试，以确保您的逻辑方程遵循此方法，而不是对状态位的非法（非独热）组合执行其他操作（例如重置FSM）。
虽然知道这个算法对于RTL级设计不是必需的（逻辑合成器处理这个问题），但它说明了为什么单热FSM通常具有更简单的逻辑（以牺牲更多的状态位存储为代价），并且这个主题经常出现在数字逻辑课程的考试中。
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (state[A]&~in) | (state[C] & ~in);
assign next_state[B] = (state[A]&in) | (state[D]&in) | (state[B]&in);
assign next_state[C] = (state[B]&~in) | (state[D]&~in);
assign next_state[D] = (state[C]&in);
// Output logic:
assign out = (state[D]);
endmodule
Simple FSM 3(asynchronous reset)
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
reg [1:0]state,next_state;
// State transition logic
always@(*)begin
case(state)
A:begin
if(in)begin
next_state=B;
end
else begin
next_state=A;
end
end
B:begin
if(in)begin
next_state=B;
end
else begin
next_state=C;
end
end
C:begin
if(in)begin
next_state=D;
end
else begin
next_state=A;
end
end
D:begin
if(in)begin
next_state=B;
end
else begin
next_state=C;
end
end
endcase
end
always@(posedge clk,posedge areset)begin
if(areset)begin
state<=A;
end
else begin
state<=next_state;
end
end
assign out=(state==D);
// State flip-flops with asynchronous reset
// Output logic
endmodule
Simple FSM 3 (synchronous reset)
module top_module(
input clk,
input in,
input reset,
output out); //
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
reg [1:0]state,next_state;
// State transition logic
always@(*)begin
case(state)
A:begin
if(in)begin
next_state=B;
end
else begin
next_state=A;
end
end
B:begin
if(in)begin
next_state=B;
end
else begin
next_state=C;
end
end
C:begin
if(in)begin
next_state=D;
end
else begin
next_state=A;
end
end
D:begin
if(in)begin
next_state=B;
end
else begin
next_state=C;
end
end
endcase
end
always@(posedge clk)begin
if(reset)begin
state<=A;
end
else begin
state<=next_state;
end
end
assign out=(state==D);
endmodule
Design a Moore FSM
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter S0=4'd1,S1=4'd2,S2=4'd4,S3=4'd8;
reg [3:0] present_state,next_state;
//state transition logic
always@(*)begin
case(present_state)
S0:begin
if(s[1]&&(~s[2])&&(~s[3]))
next_state = S1;
else
next_state = S0;
end
S1:begin
if(s[1]==1&&s[2]==1&&s[3]==0)
next_state = S2;
else if(s[1]==1&&s[2]==0&&s[3]==0)
next_state = S1;
else
next_state = S0;
end
S2:begin
if(s[1]==1&&s[2]==1&&s[3]==1)
next_state = S3;
else if(s[1]==1&&s[2]==0&&s[3]==0)
next_state = S1;
else
next_state = S2;
end
S3:begin
if(s[1]==1&&s[2]==1&&s[3]==1)
next_state = S3;
else
next_state = S2;
end
endcase
end
always@(posedge clk)
if(reset)
present_state <= S0;
else
present_state <= next_state;
reg state_lower;
always@(posedge clk)begin
if(reset||present_state<next_state)
state_lower <= 1'b0;
else if(present_state>next_state)
state_lower <= 1'b1;
end
assign dfr = (present_state==S0)||(state_lower);
always@(*)begin
if(present_state == S0)begin
{fr3,fr2,fr1}=3'b111;
end
else if(present_state == S1)begin
{fr3,fr2,fr1}=3'b011;
end
else if(present_state == S2)begin
{fr3,fr2,fr1}=3'b001;
end
else if(present_state == S3)begin
{fr3,fr2,fr1}=3'b0;
end
end
endmodule
(33条消息) HDLBits状态机练习题目 water reservoir蓄水池控制器sensors asserted鱼禹的博客-CSDN博客
Lemmings 1
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //
parameter LEFT=1'b0,RIGHT=1'b1;
// parameter LEFT=0, RIGHT=1, ...
reg state, next_state;
wire [1:0]bump;
assign bump={bump_left,bump_right};
always @(*) begin
// State transition logic
case(state)
LEFT:begin
if(bump==2'b10||bump==2'b11)begin
next_state=RIGHT;
end
else begin
next_state=LEFT;
end
end
RIGHT:begin
if(bump==2'b11||bump==2'b01)begin
next_state=LEFT;
end
else begin
next_state=RIGHT;
end
end
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state<=LEFT;
end
else begin
state<=next_state;
end
end
// Output logic
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
这一题有点意思的在于不用考虑小人怎么会是左右同时撞墙的，他是怎么走进去的
Lemmings 2
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
parameter LEFT=2'b00,RIGHT=2'b01,LEFT_F=2'b10,RIGHT_F=2'b11;
reg [3:0]state,next_state;
wire [1:0]bump;
assign bump={bump_left,bump_right};
always@(*)begin
case(state)
LEFT:begin
if(ground==1'b0)begin
next_state=LEFT_F;
end
else if(ground==1'b1)begin
if(bump==2'b11||bump==2'b10)begin
next_state=RIGHT;
end
else begin
next_state=LEFT;
end
end
end
RIGHT:begin
if(ground==1'b0)begin
next_state=RIGHT_F;
end
else if(ground==1'b1)begin
if(bump==2'b11||bump==2'b01)begin
next_state=LEFT;
end
else begin
next_state=RIGHT;
end
end
end
LEFT_F:begin
if(ground==1'b0)begin
next_state=LEFT_F;
end
else if(ground==1'b1)begin
next_state=LEFT;
end
end
RIGHT_F:begin
if(ground==1'b0)begin
next_state=RIGHT_F;
end
else if(ground==1'b1)begin
next_state=RIGHT;
end
end
endcase
end
always@(posedge clk,posedge areset)begin
if(areset)begin
state<=LEFT;
end
else begin
state<=next_state;
end
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign aaah=(state==LEFT_F||state==RIGHT_F);
endmodule
挺有意思的，状态机的关键在于对于不同状态的分析，进而得到状态转换图
HDLBits (129) — 旅鼠 2 - 哔哩哔哩 (bilibili.com)
Lemming 3
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter LEFT = 0, RIGHT = 1, FALL_L = 2, FALL_R = 3, DIG_L = 4, DIG_R = 5;
reg [2:0] state, next_state;
always @(posedge clk or posedge areset) begin
if (areset)
state <= LEFT;
else
state <= next_state;
end
always @(*) begin
case (state)
LEFT : next_state <= ground ? (dig ? DIG_L: (bump_left ? RIGHT : LEFT)) :FALL_L;
RIGHT : next_state <= ground ? (dig ? DIG_R: (bump_right ? LEFT : RIGHT)) :FALL_R;
FALL_L : next_state <= ground ? LEFT : FALL_L;
FALL_R : next_state <= ground ? RIGHT : FALL_R;
DIG_L : next_state <= ground ? DIG_L : FALL_L;
DIG_R : next_state <= ground ? DIG_R : FALL_R;
endcase
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign aaah = ((state == FALL_L) || (state == FALL_R));
assign digging = ((state == DIG_L) || (state == DIG_R));
endmodule
HDLBits (130) — 旅鼠 3 - 哔哩哔哩 (bilibili.com)
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter left=3'd0, right=3'd1, falll=3'd2, fallr=3'd3, digl=3'd4, digr=3'd5, splat=3'd6;
reg [2:0] state, next_state;
reg [31:0] count;
always@(posedge clk or posedge areset) begin
if(areset)
state <= left;
else if(state == falll || state == fallr) begin
state <= next_state;
count <= count + 1;
end
else begin
state <= next_state;
count <= 0;
end
end
always@(*) begin
case(state)
left: begin
if(~ground) next_state = falll;
else if(dig) next_state = digl;
else if(bump_left) next_state = right;
else next_state = left;
end
right: begin
if(~ground) next_state = fallr;
else if(dig) next_state = digr;
else if(bump_right) next_state = left;
else next_state = right;
end
falll: begin
if(ground) begin
if(count>19) next_state = splat;
else next_state = left;
end
else next_state = falll;
end
fallr: begin
if(ground) begin
if(count>19) next_state = splat;
else next_state = right;
end
else next_state = fallr;
end
digl: begin
if(ground) next_state = digl;
else next_state = falll;
end
digr: begin
if(ground) next_state = digr;
else next_state = fallr;
end
splat: begin
next_state = splat;
end
endcase
end
assign walk_left = (state == left);
assign walk_right = (state == right);
assign aaah = (state == falll || state == fallr);
assign digging = (state == digl || state == digr);
endmodule
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