基于SparkRoad的Hdlbits学习（9）

龙场悟道

[4-bit shift register](Shift4 - HDLBits (01xz.net))

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    //areset：让寄存器复位为0
	//load：加载4bit数据到移位寄存器中，不移位
	//ena：使能右移
	//q：移位寄存器中的内容
    always@(posedge clk,posedge areset)begin   //因为是异步复位
        if(areset)begin
            q<=4'b0;
        end
        else if(load)begin
            q<=data;
        end
        else if(ena)begin
            q<={1'b0,q[3:1]};
        end
        else begin
            q<=q;   //不改变q
        end
    end
endmodule

[Left/right rotator](Rotate100 - HDLBits (01xz.net))

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q);
    
    always @(posedge clk) begin
        if(load) begin
            q <= data;
        end
        else begin
            case (ena)
                2'b01:q <= {q[0],q[99:1]};
                2'b10:q <= {q[98:0],q[99]};
                default:q <= q;
            endcase
        end
    end
endmodule

[Left/right arithmetic shift by 1 or 8](Shift18 - HDLBits (01xz.net))

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always@(posedge clk)begin
        if(load)begin
            q<=data;
        end
        else begin
            if(ena)begin
                case(amount)
                    2'b00:q<={q[62:0],1'b0};
                    2'b01:q<={q[55:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
                    2'b10:q<={q[63],q[63:1]};
                    2'b11:q<={{8{q[63]}},q[63:8]};
                endcase
            end
            else begin
                q<=q;
            end
        end
    end
endmodule

[5-bit LFSR](Lfsr5 - HDLBits (01xz.net))

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
    ); 
    always@(posedge clk)begin
        if(reset)begin
            q<=5'h1;
        end
        else begin
            q[4]<=1'b0^q[0];
            q[3]<=q[4];
            q[2]<=q[3]^q[0];
            q[1]<=q[2];
            q[0]<=q[1];
        end
    end
endmodule

[3-bit LFSR](Mt2015 lfsr - HDLBits (01xz.net))

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    wire clk;
    assign clk = KEY[0];
    
    always @(posedge clk)begin
        if(KEY[1])begin
            LEDR[0] <= SW[0];
            LEDR[1] <= SW[1];
            LEDR[2] <= SW[2];
        end
        else begin
            LEDR[0] <= LEDR[2];
            LEDR[1] <= LEDR[0];
            LEDR[2] <= LEDR[2] ^ LEDR[1];
        end
    end
endmodule

[32-bit LFSR](Lfsr32 - HDLBits (01xz.net))

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
    ); 
    
    reg [31:0] q1;
        always@(posedge clk) begin
            if(reset) q1 <= 32'h1;
        else begin
            q1 <= {q1[0],q1[31:23],q1[0]^q1[22],q1[21:3],q1[0]^q1[2],q1[0]^q1[1]};
        end
        
    end
    assign q = q1;
endmodule

![[1686137880838.png]] 在此基础上再增加 taps，即在那几个位置增加异或即可
[Shift register](Exams/m2014 q4k - HDLBits (01xz.net))

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg [3:0]q;
    assign out=q[3];
    always@(posedge clk)begin
        if(!resetn)begin
            q<=4'b0;
        end
        else begin
            q[3]<=q[2];
            q[2]<=q[1];
            q[1]<=q[0];
            q[0]<=in;
        end
    end            
endmodule

但是如果如下写就会报错

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg [3:0]q;
    always@(posedge clk)begin
        if(!resetn)begin
            q<=4'b0;
        end
        else begin
            out<=q[3];
            q[3]<=q[2];
            q[2]<=q[1];
            q[1]<=q[0];
            q[0]<=in;
        end
    end            
endmodule

![[1686139455793.png]] 可能是因为 out 的非阻塞语句在 always 中延迟了一个周期输出导致
[Shift register](Exams/2014 q4b - HDLBits (01xz.net))

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
    ); 
    
    MUXDFF u1(.clk(KEY[0]),
               .w(KEY[3]),
               .R(SW[3]),
               .E(KEY[1]),
               .L(KEY[2]),
               .Q(LEDR[3]));
    
    MUXDFF u2(.clk(KEY[0]),
               .w(LEDR[3]),
               .R(SW[2]),
               .E(KEY[1]),
               .L(KEY[2]),
               .Q(LEDR[2]));
    
    MUXDFF u3(.clk(KEY[0]),
               .w(LEDR[2]),
               .R(SW[1]),
               .E(KEY[1]),
               .L(KEY[2]),
               .Q(LEDR[1]));
    
    MUXDFF u4(.clk(KEY[0]),
               .w(LEDR[1]),
               .R(SW[0]),
               .E(KEY[1]),
               .L(KEY[2]),
               .Q(LEDR[0]));
endmodule
module MUXDFF (
    input clk,
    input w,R,E,L,
    output Q
    );
    wire tmp;
    assign tmp = E ? w : Q;
    always @(posedge clk)begin
        Q <= L? R : tmp;
    end
endmodule

[3-input LUT](Exams/ece241 2013 q12 - HDLBits (01xz.net))

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
	reg [7:0] Q;
    always @(posedge clk)begin
        if(enable)begin
            Q <= {Q[6:0],S};
        end
        else begin
            Q <= Q;
        end
    end
    
    assign Z = Q[{A,B,C}];
endmodule