[2-to-1 multiplexer](Mux2to1 - HDLBits (01xz.net))
module top_module(
input a, b, sel,
output out );
always@*begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
[2-to-1 bus multiplexer](Mux2to1v - HDLBits (01xz.net))
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
always@*begin
case(sel) //这里的case注意并没有begin需要跟随,如果跟随了,反而会报错
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
[9-to-1 multiplexer](Mux9to1v - HDLBits (01xz.net))
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always@*begin
case(sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default:out = 16'hffff;
endcase
end
endmodule
[256-to-1 multiplexer](Mux256to1 - HDLBits (01xz.net))
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
//创建一个位宽为1的256-1的多路选择器。256个输入都被打包成一个256位的输入向量。sel=0表示选择in[0],sel=1表示选择in[1],以此类推。
endmodule
[256-to-1 4-bit multiplexer](Mux256to1v - HDLBits (01xz.net))
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
endmodule
[Half adder](Hadd - HDLBits (01xz.net))
module top_module(
input a, b,
output cout, sum );
assign cout=a&b;
assign sum=a^b;
endmodule
[Full adder](Fadd - HDLBits (01xz.net))
module top_module(
input a, b, cin,
Output cout, sum );
assign sum=a^b^cin;
assign cout=(a&b)|(a&cin)|(cin&b);
endmodule
[3-bit binary adder](Adder3 - HDLBits (01xz.net))
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
assign {cout[0],sum[0]} = a[0] + b[0] +cin;
assign {cout[1],sum[1]} = a[1] + b[1] +cout[0];
assign {cout[2],sum[2]} = a[2] + b[2] +cout[1];
endmodule
[Adder](Exams/m2014 q4j - HDLBits (01xz.net))
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
wire [2:0] cout;
assign {cout[0],sum[0]}=x[0]+y[0];
assign {cout[1],sum[1]}=x[1]+y[1]+cout[0];
assign {cout[2],sum[2]} = x[2] + y[2] + cout[1];
assign {sum[4],sum[3]} = x[3] + y[3] + cout[2];
endmodule
[Singned addition overflow](Exams/ece241 2014 q1c - HDLBits (01xz.net))
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
assign s = a + b; //不用每个位单独写
assign overflow = (a[7]&b[7]&~s[7]) | ((~a[7])&(~b[7])&s[7]);
// assign s = ...
// assign overflow = ...
endmodule
[100-bit binary adder](Adder100 - HDLBits (01xz.net))
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout,sum[99:0]} = a + b + cin;
endmodule
[4-digit BCD adder](Bcdadd4 - HDLBits (01xz.net))
module top_module (
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [2:0] cout_temp;
bcd_fadd bcd_1(a[3:0],b[3:0],cin,cout_temp[0],sum[3:0]);
bcd_fadd bcd_2(a[7:4],b[7:4],cout_temp[0],cout_temp[1],sum[7:4]);
bcd_fadd bcd_3(a[11:8],b[11:8],cout_temp[1],cout_temp[2],sum[11:8]);
bcd_fadd bcd_4(a[15:12],b[15:12],cout_temp[2],cout,sum[15:12]);
endmodule
[3-variable](Kmap1 - HDLBits (01xz.net))
module top_module(
input a,
input b,
input c,
output out );
assign out = ~((~a)&(~b)&(~c));
endmodule
[4-variable (1)](Kmap2 - HDLBits (01xz.net))
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a & ~d | ~b & ~c | b & c & d | a & c & d;
endmodule
[4-variable (2)](Kmap3 - HDLBits (01xz.net))
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a | (~a&~b&c);
endmodule
[4-variable(3)](Kmap4 - HDLBits (01xz.net))
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a & b & ~c & ~d | a & ~b & ~c & ~d |
~a & ~b & ~c & d | a & b & ~c & d |
~a & b & c & d | a & ~b & c & d |
~a & ~b & c & ~d | a & b & c & ~d;
endmodule
[Minimum SOP and POS](Exams/ece241 2013 q2 - HDLBits (01xz.net))
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c & d | ~a & ~b & c;
assign out_pos = ~((~c | ~d) & (a | b | ~c));
endmodule
[Karnaugh map (1)](Exams/m2014 q3 - HDLBits (01xz.net))
module top_module (
input [4:1] x,
output f );
assign f = ~x[1]&x[3] | x[2]&x[4];
endmodule
[Karnaugh map (2)](Exams/2012 q1g - HDLBits (01xz.net))
module top_module (
input [4:1] x,
output f
);
assign f = ~x[2]&~x[4] | ~x[1]&x[3] | x[2]&x[3]&x[4];
endmodule
[K-map implemented with a multiplexer](Exams/ece241 2014 q3 - HDLBits (01xz.net))
module top_module (
input c,
input d,
output [3:0] mux_in
);
always @(*) begin
case({c,d})
2'b0:
mux_in = 4'b0100;
2'b1:
mux_in = 4'b0001;
2'b11:
mux_in = 4'b1001;
default:
mux_in = 4'b0101;
endcase
end
endmodule
反思:
- 组合电路的部分完成了,下面准备复习重要的时序逻辑电路了
- 准备对组合电路中的两种加法器进行 SparkRoad 实物设计