![](https://verimake.com/assets/files/2023-04-07/1680861037-832338-b338320b0768f6a1452aff196e40ace.jpg)
正弦波、方波、三角波
module waveform_generator(
input wire clk,
input wire reset,
input wire [1:0] waveform_select, // 2位输入选择波形(00:正弦波,01:方波,10:三角波)
output reg [7:0] waveform_out
);
reg [31:0] phase_accumulator = 32'h0; // 32位相位累加器
reg [31:0] phase_increment = 32'h051EB851; // 32位相位增量
// 查找表数组
reg [7:0] sine_lut[0:255];
reg [7:0] square_lut[0:255];
reg [7:0] triangle_lut[0:255];
// 从文件加载查找表
initial begin
$readmemh("sine_lut.hex", sine_lut);
$readmemh("square_lut.hex", square_lut);
$readmemh("triangle_lut.hex", triangle_lut);
end
always @(posedge clk or posedge reset) begin
if (reset) begin
phase_accumulator <= 32'h0;
end else begin
phase_accumulator <= phase_accumulator + phase_increment;
end
end
// 根据输入选择波形
always @(*) begin
case (waveform_select)
2'b00: waveform_out = sine_lut[phase_accumulator[31:24]];
2'b01: waveform_out = square_lut[phase_accumulator[31:24]];
2'b10: waveform_out = triangle_lut[phase_accumulator[31:24]];
default: waveform_out = 8'h00;
endcase
end
endmodule
心形波形
module heart_waveform_generator(
input wire clk,
input wire reset,
output reg [7:0] heart_wave_x,
output reg [7:0] heart_wave_y
);
reg [31:0] phase_accumulator = 32'h0; // 32位相位累加器
reg [31:0] phase_increment = 32'h051EB851; // 32位相位增量
// 查找表数组
reg [7:0] heart_lut_x[0:255];
reg [7:0] heart_lut_y[0:255];
// 从文件加载查找表
initial begin
$readmemh("heart_lut_x.hex", heart_lut_x);
$readmemh("heart_lut_y.hex", heart_lut_y);
end
always @(posedge clk or posedge reset) begin
if (reset) begin
phase_accumulator <= 32'h0;
end else begin
phase_accumulator <= phase_accumulator + phase_increment;
end
end
// 输出心形波形的x和y值
always @(*) begin
heart_wave_x = heart_lut_x[phase_accumulator[31:24]];
heart_wave_y = heart_lut_y[phase_accumulator[31:24]];
end
endmodule